1. Field of the Invention
The present invention relates to a bipolar transistor and a semiconductor device having the same, and in particular to a bipolar transistor manufactured by a process, from which formation of a heavily doped buried diffusion layer is omitted, as well as a semiconductor device having the bipolar transistor.
2. Description of the Background Art
An example of a semiconductor device having a bipolar transistor in the prior art is shown in FIG. 14. The semiconductor device shown in FIG. 14 is disclosed at FIG. 1(d) in Japanese Patent Laying-Open No. 61-230354 (1986).
Referring to FIG. 14, a p-type semiconductor substrate 21 is provided at its main surface with an n-type epitaxial layer 23. n.sup.+ -buried diffusion layers 22a and 22b are selectively formed at the bottom of n-type epitaxial layer 23. An isolation region 24 and a p-well region 25 are formed at predetermined positions of n-type epitaxial layer 23.
Isolation oxide films 29 are selectively formed at the surface of n-type epitaxial layer 23. A base region 28, an external base region 28a, an emitter region 35 and an n.sup.+ -diffusion layer 26c are formed at the surface of n-type epitaxial layer (collector region) 23 located above n.sup.+ -buried diffusion layer 22a. In the state shown in FIG. 14, a polycrystalline silicon layer 33 is formed on base region 28 and emitter region 35.
A pMOS transistor is formed at the surface of n-type epitaxial layer 23 located above n.sup.+ -buried diffusion layer 22b. The pMOS transistor has a pair of p.sup.+ -diffusion layers 27a and 27b as well as a gate electrode 30b.
An nMOS transistor is formed at the surface of p-well region 25. The nMOS transistor has a pair of n.sup.+ -diffusion layers 26a and 26b as well as a gate electrode 30a. Gate electrodes 30a and 30b are covered with insulating layers 31, over which insulating layers 32 are formed. Insulating layers 32 are also formed over isolating oxide films 29.
In the above semiconductor device, n.sup.+ -buried diffusion layer 22a is formed for reducing a collector resistance, as shown in FIG. 14. Formation of n.sup.+ -buried diffusion layer 22a requires various steps such as a photolithographic step and an ion implanting step, resulting in remarkable increase of a manufacturing cost. Therefore, it is desired to eliminate formation of n.sup.+ -buried diffusion layer 22a for reducing the manufacturing cost. FIG. 15 shows an example of a bipolar transistor manufactured by a process, from which formation of the n.sup.+ -buried diffusion layer is omitted. This bipolar transistor is the same as that disclosed in Japanese Patent Laying-Open No. 59-121864 (1984).
Referring to FIG. 15, p-type semiconductor substrate 21 is provided at its main surface with an n-well region 34. p-type base region 28 is formed at the surface of n-well region 34. An emitter region 35 is formed at the surface of base region 28.
At the surface of n-well region 34, there is formed an n.sup.+ -diffusion layer 26c spaced from base region 28. n.sup.+ -diffusion layer 26c has a diffusion depth larger than that of emitter region 35 as shown in FIG. 15. Thereby, the collector resistance can be reduced.
n.sup.+ -diffusion layer 26c is formed at the same diffusion step as emitter region 35, and impurities introduced into n.sup.+ -diffusion layer 26c and emitter region 35 are selected so that the diffusion coefficient of impurity introduced into n.sup.+ -diffusion layer 26c is larger than that introduced into the emitter region 35. As described above, polycrystalline silicon layer 36 doped with impurity different from that introduced into emitter region 35 is formed on the surface of n.sup.+ -diffusion layer 26c.
An insulating layer 38 having openings at predetermined positions is formed on the main surface of semiconductor substrate 1. A collector electrode 37a, an emitter electrode 37b and a base electrode 37c are formed in these openings, respectively.
In the process of manufacturing the bipolar transistor shown in FIG. 15, formation of the n.sup.+ -buried diffusion layer is omitted, so that the manufacturing cost can be smaller than that of the structure shown in FIG. 14. Due to elimination of the n.sup.+ -buried diffusion layer, however, the collector resistance of the bipolar transistor shown in FIG. 15 is larger than that of the bipolar transistor shown in FIG. 14. Even the bipolar transistor having a relatively high collector resistance can be used in a circuit performing a small-amplitude operation. More specifically, a circuit such as a differential circuit in a sense amplifier of an SRAM (Static Random Access Memory) can use such a bipolar transistor having a relatively high collector resistance.
A structure and an operation of a differential circuit will be described below with reference to FIG. 16. FIG. 16 is an equivalent circuit diagram showing an example of the differential circuit. Referring to FIG. 16, a pair of npn transistors Q1 and Q2 are connected to have a common emitter. The emitter is connected to a constant current supply (500 .mu.A) 20. Collectors of npn bipolar transistors Q1 and Q2 are connected to a power supply Vcc via resistances R1 and R2 each having a resistance of 600 .OMEGA., respectively. An input terminal Vin1 is connected to a base of npn bipolar transistor Q1. An input terminal Vin2 is connected to a base of npn bipolar transistor Q2. Output terminals Vout1 and Vout2 are connected to collectors of npn bipolar transistors Q1 and Q2, respectively. Output terminals Vout1 and Vout2 are grounded via capacitors C1 and C2 each having a capacitance of 0.5 pF, respectively.
In the above differential circuit, when a voltage applied to input terminal Vin1 is higher than a voltage applied to input terminal Vin2, a current flows through bipolar transistor Q1. Thereby, the potential on output terminal Vout1 is lower than that on output terminal Vout2. When the voltage applied to input terminal Vin1 is lower than the voltage applied to input terminal Vin2, the potential on output terminal Vout1 is higher than that on output terminal Vout2.
It is considered that the bipolar transistor shown in FIG. 15 can be used in the differential circuit having the structure and operation described above. However, the following point must be taken into consideration when using the bipolar transistor.
FIG. 17 shows a relationship between a current amplification efficiency (h.sub.FE) and a collector current (Ic). When using the bipolar transistor in the differential circuit shown in FIG. 16, it is desired that collector current Ic is about 500 .mu.A. In order to obtain the stable value of h.sub.FE with collector current Ic of the above value, a collector resistance Rc must be 250 .OMEGA. or less as shown in FIG. 17. If collector resistance Rc is larger than 250 .OMEGA., the stable value of h.sub.FE cannot be obtained with collector current Ic of 500 .mu.A.
Meanwhile, collector resistance Rc can be reduced in the bipolar transistor shown in FIG. 15 by forming deep n.sup.+ -diffusion layer 26c as already described. This enables use in the differential circuit shown in FIG. 16.
However, even the bipolar transistor shown in FIG. 15 suffers from the following problem. In the bipolar transistor shown in FIG. 15, impurity for forming emitter region 35 must be different from that for forming n.sup.+ -diffusion layer 26c. Therefore, formation of n.sup.+ -diffusion layer 26c requires a step of newly forming polycrystalline silicon layer 36 doped with impurity which is different from that used for forming emitter region 35. This results in a complicated manufacturing process and thus a high manufacturing cost.